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author | 2023-07-15 11:06:20 +0800 | |
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committer | 2023-07-25 12:10:00 +0100 | |
commit | f85739c0b2b0d98a32f5ca4fcc5501d2b76df4f6 (patch) | |
tree | e27eff67f24fb4af9be81207923a8100bc9acd7e /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ASoC: rt711-sdca: fix for JD event handling in ClockStop Mode0 (diff) | |
download | wireguard-linux-f85739c0b2b0d98a32f5ca4fcc5501d2b76df4f6.tar.xz wireguard-linux-f85739c0b2b0d98a32f5ca4fcc5501d2b76df4f6.zip |
ASoC: atmel: Fix the 8K sample parameter in I2SC master
The 8K sample parameter of 12.288Mhz main system bus clock doesn't work
because the I2SC_MR.IMCKDIV must not be 0 according to the sama5d2
series datasheet(I2SC Mode Register of Register Summary).
So use the 6.144Mhz instead of 12.288Mhz to support 8K sample.
Signed-off-by: Guiting Shen <aarongt.shen@gmail.com>
Link: https://lore.kernel.org/r/20230715030620.62328-1-aarongt.shen@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions