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| author |   Kan Liang <kan.liang@linux.intel.com> | 2021-06-30 14:08:29 -0700 |
|---|---|---|
| committer |   Peter Zijlstra <peterz@infradead.org> | 2021-07-02 15:58:38 +0200 |
| commit | f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7 (patch) | |
| tree | 554bc6eb9a4d2d2b3c462b5e067fa71f110af067 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | perf/x86/intel/uncore: Add Sapphire Rapids server IRP support (diff) | |
| download | wireguard-linux-f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7.tar.xz wireguard-linux-f85ef898f8842b2a9a8f51a64eaf45ee2a8bb1f7.zip | |
perf/x86/intel/uncore: Add Sapphire Rapids server M2PCIe support
M2PCIe* blocks manage the interface between the mesh and each IIO stack.
The layout of the control registers for a M2PCIe uncore unit is similar
to a IRP uncore unit.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-6-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions