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author | 2021-06-01 05:31:17 +0300 | |
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committer | 2021-06-02 10:58:42 +0200 | |
commit | f880ee9e96887786dc21e9433ede1719bc3b2624 (patch) | |
tree | 53c10260866e262803954ccb38f6a42b9b5c8e0d /tools/perf/scripts/python/export-to-postgresql.py | |
parent | soc/tegra: fuse: Add stubs needed for compile-testing (diff) | |
download | wireguard-linux-f880ee9e96887786dc21e9433ede1719bc3b2624.tar.xz wireguard-linux-f880ee9e96887786dc21e9433ede1719bc3b2624.zip |
soc/tegra: pmc: Add core power domain
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a level which satisfies all devices within the power domain.
Add support for the core power domain which controls voltage state of the
domain. This allows us to support system-wide DVFS on Tegra20-210 SoCs.
The PMC powergate domains now are sub-domains of the core domain, this
requires device-tree updating, older DTBs are unaffected and will continue
to work as before.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[treding@nvidia.com: squash lockdep class removal patch]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions