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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2023-08-29 11:03:54 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-08-29 11:03:54 -0500 |
| commit | fa8805ad67fa484f8f15ee74309aedef0f4b4982 (patch) | |
| tree | c656d9bdda6f1975eacbd59ee842810d4cc47e9e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'pci/controller/microchip' (diff) | |
| parent | dt-bindings: PCI: qcom: Fix SDX65 compatible (diff) | |
| download | wireguard-linux-fa8805ad67fa484f8f15ee74309aedef0f4b4982.tar.xz wireguard-linux-fa8805ad67fa484f8f15ee74309aedef0f4b4982.zip | |
Merge branch 'pci/controller/qcom'
- Configure controller so MHI bus master clock will be switched off while
in ASPM L1.x states (Manivannan Sadhasivam)
- Add sa8775p DT binding and driver support (Mrinmay Sarkar)
- Fix broken DT SDX65 "compatible" property (Krzysztof Kozlowski)
* pci/controller/qcom:
dt-bindings: PCI: qcom: Fix SDX65 compatible
PCI: qcom: Add support for sa8775p SoC
dt-bindings: PCI: qcom: Add sa8775p compatible
PCI: qcom-ep: Switch MHI bus master clock off during L1SS
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions