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| author |   Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-01-05 14:59:38 -0600 |
|---|---|---|
| committer |   Dinh Nguyen <dinguyen@kernel.org> | 2016-04-11 13:47:22 -0500 |
| commit | faf68cdfdf6c9f0999686802ad066b1378b89413 (patch) | |
| tree | e2bbd8f97d29c3bf1c1e5955277f963c3cb52183 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node (diff) | |
| download | wireguard-linux-faf68cdfdf6c9f0999686802ad066b1378b89413.tar.xz wireguard-linux-faf68cdfdf6c9f0999686802ad066b1378b89413.zip | |
ARM: dts: socfpga: add the clk-phase property for sd/mmc clock
The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions