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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-08-10 13:35:03 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-08-10 13:35:03 +0200 |
| commit | fb210df33dd969a5cc16aeba809c5e89430f7c4e (patch) | |
| tree | 130591815d485dd6f1d4398e5cdc56f4070f42e5 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: renesas: r9a07g044: Add ADC node (diff) | |
| parent | dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock (diff) | |
| download | wireguard-linux-fb210df33dd969a5cc16aeba809c5e89430f7c4e.tar.xz wireguard-linux-fb210df33dd969a5cc16aeba809c5e89430f7c4e.zip | |
Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into HEAD
Renesas RZ/G2L DT Binding Definitions Update
Missing definition for the P0_DIV2 core clock on the Renesas RZ/G2L
(R9A07G044) SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions