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| author |   Imre Deak <imre.deak@intel.com> | 2020-06-29 21:58:48 +0300 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2020-07-01 15:39:00 +0300 |
| commit | fc6200948275383ca214bb30dd175dfd0d61149b (patch) | |
| tree | 4fdb4ee6a2f04c65f019ee9efa3ebfb613db7169 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock (diff) | |
| download | wireguard-linux-fc6200948275383ca214bb30dd175dfd0d61149b.tar.xz wireguard-linux-fc6200948275383ca214bb30dd175dfd0d61149b.zip | |
drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain
To simplify things, call the combo PHY/TBT PLL calculation functions
directly from the corresponding combo/TypeC PLL get functions, instead of
calling the same calculation functions after having to recheck if the
given PHY is combo or TypeC.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200629185848.20550-2-imre.deak@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions