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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:43 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:43 -0500 |
| commit | fd0c51f7eb4b4ad9d7ed971757e76ce3fe346c85 (patch) | |
| tree | f5cb25cb0f5f3e0d59194ce3cd830b73c49a243f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'pci/controller/rcar-gen4' (diff) | |
| parent | PCI: rockchip-ep: Mark RK3399 as intx_capable (diff) | |
| download | wireguard-linux-fd0c51f7eb4b4ad9d7ed971757e76ce3fe346c85.tar.xz wireguard-linux-fd0c51f7eb4b4ad9d7ed971757e76ce3fe346c85.zip | |
Merge branch 'pci/controller/rockchip'
- Reorder rockchip_pci_core_rsts because reset_control_bulk_deassert()
deasserts in reverse order, to fix a link training regression (Jensen
Huang)
- Mark RK3399 as being capable of raising INTx interrupts (Niklas Cassel)
* pci/controller/rockchip:
PCI: rockchip-ep: Mark RK3399 as intx_capable
PCI: rockchip: Fix order of rockchip_pci_core_rsts
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions