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| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-06-02 09:06:49 -0700 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-06-05 15:39:13 +0200 |
| commit | fe811e1de389c373ddf0671888e32f9ad973c969 (patch) | |
| tree | 7aaaf5f02ca3c36b85e99d6c549e8d28551ee785 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: r7s72100: add USB bit definitions (diff) | |
| download | wireguard-linux-fe811e1de389c373ddf0671888e32f9ad973c969.tar.xz wireguard-linux-fe811e1de389c373ddf0671888e32f9ad973c969.zip | |
ARM: dts: r7s72100: add clock bit definitions
Add the remaining bit locations for the module stop clock registers.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions