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| author |   Simon Horman <horms+renesas@verge.net.au> | 2016-07-07 10:21:07 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-07-07 10:21:07 +0200 |
| commit | fffae950cf00a60ff584618ecc939c6a931e4bbb (patch) | |
| tree | 6d3c57eb9ba4a8c63efed96719c6c0b5ea9f01a1 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: r8a7795: Drop 0x from unit address of gic (diff) | |
| parent | clk: renesas: r8a7795: Add THS/TSC clock (diff) | |
| download | wireguard-linux-fffae950cf00a60ff584618ecc939c6a931e4bbb.tar.xz wireguard-linux-fffae950cf00a60ff584618ecc939c6a931e4bbb.zip | |
Merge tag 'clk-renesas-for-v4.8-tag2' into HEAD
clk: renesas: Updates for v4.8 (take two)
- Add support for R-Car V2H,
- Add FDP1, DRIF, and thermal clocks on R-Car H3,
- Correct a wrong parent clock.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions