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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-02-13 09:01:21 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-02-13 09:01:21 -0800 |
| commit | 05c3ae7aa13084d31b5109e7e8d7c74e305b325f (patch) | |
| tree | 6ccc72b5460712a28d12dba934f7267fc099e94b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: qcom: gcc: Use active only source for CPUSS clocks (diff) | |
| parent | clk: sunxi: A31: Fix wrong AHB gate number (diff) | |
| download | wireguard-linux-05c3ae7aa13084d31b5109e7e8d7c74e305b325f.tar.xz wireguard-linux-05c3ae7aa13084d31b5109e7e8d7c74e305b325f.zip | |
Merge tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-fixes
Pull Allwinner clock fixes from Maxime Ripard:
Two fixes for clock indices, one for the A31 and one for the V3s.
* tag 'sunxi-clk-fixes-for-5.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi: A31: Fix wrong AHB gate number
clk: sunxi-ng: v3s: Fix TCON reset de-assert bit
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions