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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2023-07-06 16:30:47 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-25 11:41:09 +0200 |
| commit | 10ca61c6c0fff0985348cc07be0bb037c0bbf15a (patch) | |
| tree | 0d0edce13e39ff1fb3870d0a1e635fab2a93e961 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: renesas: Add missing space before { (diff) | |
| download | wireguard-linux-10ca61c6c0fff0985348cc07be0bb037c0bbf15a.tar.xz wireguard-linux-10ca61c6c0fff0985348cc07be0bb037c0bbf15a.zip | |
arm64: dts: renesas: rzg2l-smarc: Add support for enabling MTU3
Add support for PMOD_MTU3 macro to enable MTU3 node on RZ/{G2,V2}L SMARC
EVK.
The MTU3a PWM pins are muxed with spi1 pins and counter external input
phase clock pins are muxed with scif2 pins. Disable these IPs when
PMOD_MTU3 macro is enabled.
Apart from this, the counter Z phase clock signal is muxed with the
SDHI1 cd signal. So disable SDHI1 IP, when the counter Z phase signal
is enabled.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230706153047.368993-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions