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author | 2024-01-03 13:34:45 +0200 | |
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committer | 2024-01-04 16:56:54 -0800 | |
commit | 14d0681b3ae2cb5c3f2fe4ca2d0b9c517f225e48 (patch) | |
tree | b322cc7e8a047f57a33215a36465ee004920fde6 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | Revert "Introduce PHY listing and link_topology tracking" (diff) | |
download | wireguard-linux-14d0681b3ae2cb5c3f2fe4ca2d0b9c517f225e48.tar.xz wireguard-linux-14d0681b3ae2cb5c3f2fe4ca2d0b9c517f225e48.zip |
net: enetc: allow phy-mode = "1000base-x"
The driver code proper is handled by the lynx_pcs. The enetc just needs
to populate phylink's supported_interfaces array, and return true for
this phy-mode in enetc_port_has_pcs(), such that it creates an internal
MDIO bus through which the Lynx PCS registers are accessed.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Link: https://lore.kernel.org/r/20240103113445.3892971-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions