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| author |   Brijesh Singh <brijesh.singh@amd.com> | 2022-02-22 22:35:28 -0600 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2022-02-23 19:14:29 +0100 |
| commit | 1e8c5971c249893ac33ca983c32bafcf5d50c727 (patch) | |
| tree | f20c6e8c3533923f1e057be90f6c26da7303cd2b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | x86/coco: Add API to handle encryption mask (diff) | |
| download | wireguard-linux-1e8c5971c249893ac33ca983c32bafcf5d50c727.tar.xz wireguard-linux-1e8c5971c249893ac33ca983c32bafcf5d50c727.zip | |
x86/mm/cpa: Generalize __set_memory_enc_pgtable()
The kernel provides infrastructure to set or clear the encryption mask
from the pages for AMD SEV, but TDX requires few tweaks.
- TDX and SEV have different requirements to the cache and TLB
flushing.
- TDX has own routine to notify VMM about page encryption status change.
Modify __set_memory_enc_pgtable() and make it flexible enough to cover
both AMD SEV and Intel TDX. The AMD-specific behavior is isolated in the
callbacks under x86_platform.guest. TDX will provide own version of said
callbacks.
[ bp: Beat into submission. ]
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: https://lore.kernel.org/r/20220223043528.2093214-1-brijesh.singh@amd.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions