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| author |   Shengjiu Wang <shengjiu.wang@nxp.com> | 2022-05-07 20:14:13 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-05-11 17:42:49 +0100 |
| commit | 292709b9cf3ba470af94b62c9bb60284cc581b79 (patch) | |
| tree | f5b5865fc87e9658f388a0954143922b436438d8 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ASoC: SOF: ipc3-topology: Correct get_control_data for non bytes payload (diff) | |
| download | wireguard-linux-292709b9cf3ba470af94b62c9bb60284cc581b79.tar.xz wireguard-linux-292709b9cf3ba470af94b62c9bb60284cc581b79.zip | |
ASoC: fsl_micfil: explicitly clear software reset bit
SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined as
non volatile register, it still remain in regmap cache after set,
then every update of REG_MICFIL_CTRL1, software reset happens.
to avoid this, clear it explicitly.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1651925654-32060-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions