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| author |   Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2018-10-23 15:09:19 +0300 |
|---|---|---|
| committer |   Vineet Gupta <vgupta@synopsys.com> | 2018-11-12 10:38:27 -0800 |
| commit | 4592f11e47a2b28562d6cfe165d5ea7495ff4dca (patch) | |
| tree | 1561b4ca6b5006ff613cca715b5f011bef23092c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ARCv2: boot log unaligned access in use (diff) | |
| download | wireguard-linux-4592f11e47a2b28562d6cfe165d5ea7495ff4dca.tar.xz wireguard-linux-4592f11e47a2b28562d6cfe165d5ea7495ff4dca.zip | |
ARC: [plat-hsdk] Enable DW APB GPIO support
Enable GPIO support on HSDK. HSDK SoC includes Synopsys
DesignWare DW_apb_gpio IP with 24 GPIOs mapped onto port A.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions