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| author |   Wesley Chalmers <Wesley.Chalmers@amd.com> | 2022-11-09 17:43:13 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-11-29 11:03:38 -0500 |
| commit | 5842abd985b792a3b13a89b6dae4869b56656c92 (patch) | |
| tree | 2c5ad29ccc58d23e80f256b42ceb490ebc1534cd /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/radeon: Fix PCI device refcount leak in radeon_atrm_get_bios() (diff) | |
| download | wireguard-linux-5842abd985b792a3b13a89b6dae4869b56656c92.tar.xz wireguard-linux-5842abd985b792a3b13a89b6dae4869b56656c92.zip | |
drm/amd/display: Use the largest vready_offset in pipe group
[WHY]
Corruption can occur in LB if vready_offset is not large enough.
DML calculates vready_offset for each pipe, but we currently select the
top pipe's vready_offset, which is not necessarily enough for all pipes
in the group.
[HOW]
Wherever program_global_sync is currently called, iterate through the
entire pipe group and find the highest vready_offset.
Reviewed-by: Dillon Varone <Dillon.Varone@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions