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| author |   Emil Renner Berthing <kernel@esmil.dk> | 2022-12-20 09:12:45 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2022-12-26 22:50:15 +0000 |
| commit | 6635e91648ce0868481fd6dd591d5ac796d8a635 (patch) | |
| tree | 4b4a7a120d6efa124c5b008e5720d0cf58eb14a0 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC (diff) | |
| download | wireguard-linux-6635e91648ce0868481fd6dd591d5ac796d8a635.tar.xz wireguard-linux-6635e91648ce0868481fd6dd591d5ac796d8a635.zip | |
soc: sifive: ccache: Add StarFive JH7110 support
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions