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| author |   Alain Volmat <avolmat@me.com> | 2021-03-31 22:42:23 +0200 |
|---|---|---|
| committer |   Patrice Chotard <patrice.chotard@foss.st.com> | 2021-08-06 09:30:02 +0200 |
| commit | 7f9ed95ddaa5ac0b8894b0fe6bb130c06cafb44d (patch) | |
| tree | 4560c1f0a78d09728078a2e00877518f949223f1 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | ARM: dts: sti: update clkgen-fsyn entries in stih407-clock (diff) | |
| download | wireguard-linux-7f9ed95ddaa5ac0b8894b0fe6bb130c06cafb44d.tar.xz wireguard-linux-7f9ed95ddaa5ac0b8894b0fe6bb130c06cafb44d.zip | |
ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions