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| author |   Paul Cercueil <paul@crapouillou.net> | 2019-03-19 15:05:35 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-04-11 13:40:58 -0700 |
| commit | 93dc07f8b089ee073075c22873ab707225e192b5 (patch) | |
| tree | a835bd2b38d36cae0a52699f6e8a7bb5dc40e736 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | Linux 5.1-rc1 (diff) | |
| download | wireguard-linux-93dc07f8b089ee073075c22873ab707225e192b5.tar.xz wireguard-linux-93dc07f8b089ee073075c22873ab707225e192b5.zip | |
dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock
Add macro for the UDC PHY clock of the JZ4725B.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions