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| author |   Duy Nguyen <duy.nguyen.rh@renesas.com> | 2024-02-01 15:19:18 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-22 11:03:32 +0100 |
| commit | ad761924be2b33555e7d6b99a0b3b0c8384f549b (patch) | |
| tree | 3fbaf964af8dacda96432d792f07c0c745ef481f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: renesas: r8a779h0: Add secondary CA76 CPU cores (diff) | |
| download | wireguard-linux-ad761924be2b33555e7d6b99a0b3b0c8384f549b.tar.xz wireguard-linux-ad761924be2b33555e7d6b99a0b3b0c8384f549b.zip | |
arm64: dts: renesas: r8a779h0: Add CPUIdle support
Support CPUIdle for ARM Cortex-A76 on R-Car V4M.
Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/848d176bdbcaf3bc44e5dae555afa9c812a19fd1.1706796979.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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