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author | 2018-07-17 15:21:56 -0700 | |
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committer | 2018-07-19 10:36:45 -0700 | |
commit | af1fc5baa724c63ce1733dfcf855bad5ef6078e3 (patch) | |
tree | a947ac298a5d3224bc2ac2c2020b85142f267ae9 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | ARC: mm: allow mprotect to make stack mappings executable (diff) | |
download | wireguard-linux-af1fc5baa724c63ce1733dfcf855bad5ef6078e3.tar.xz wireguard-linux-af1fc5baa724c63ce1733dfcf855bad5ef6078e3.zip |
ARCv2: [plat-hsdk]: Save accl reg pair by default
This manifsted as strace segfaulting on HSDK because gcc was targetting
the accumulator registers as GPRs, which kernek was not saving/restoring
by default.
Cc: stable@vger.kernel.org #4.14+
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions