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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-20 15:57:32 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-01 11:35:07 +0200 |
| commit | b1c34567aebe300f9a0f70320eaeef0b3d56ffc7 (patch) | |
| tree | a95a8d8b0a8e64c3af33298e39a7572f0a25233b /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ (diff) | |
| download | wireguard-linux-b1c34567aebe300f9a0f70320eaeef0b3d56ffc7.tar.xz wireguard-linux-b1c34567aebe300f9a0f70320eaeef0b3d56ffc7.zip | |
arm64: dts: renesas: r8a779f0: Add missing hypervisor virtual timer IRQ
Add the missing fifth interrupt to the device node that represents the
ARM architected timer. While at it, add an interrupt-names property for
clarity,
Fixes: c62331e8222f8f21 ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/46deba1008f73e4b6864f937642d17f9d4ae7205.1718890849.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions