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| author |   YueHaibing <yuehaibing@huawei.com> | 2019-03-19 23:35:04 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2019-04-11 11:46:02 -0700 |
| commit | b331db554815d0552c537e189b897eb062486166 (patch) | |
| tree | 84551df43f406a813174d981dd88405e3de595aa /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 (diff) | |
| download | wireguard-linux-b331db554815d0552c537e189b897eb062486166.tar.xz wireguard-linux-b331db554815d0552c537e189b897eb062486166.zip | |
clk: tegra: Make tegra_clk_super_mux_ops static
Fix sparse warning:
drivers/clk/tegra/clk-super.c:124:22:
warning: symbol 'tegra_clk_super_mux_ops' was not declared. Should it be static?
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions