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| author |   Guo Ren <guoren@linux.alibaba.com> | 2020-08-18 07:31:17 +0000 |
|---|---|---|
| committer |   Daniel Lezcano <daniel.lezcano@linaro.org> | 2020-08-24 13:01:39 +0200 |
| commit | bc6717d55d07110d8f3c6d31ec2af50c11b07091 (patch) | |
| tree | d4114e38242097ba13268645f9b00fe0e60c59e9 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | clocksource/drivers/timer-ti-dm: Do reset before enable (diff) | |
| download | wireguard-linux-bc6717d55d07110d8f3c6d31ec2af50c11b07091.tar.xz wireguard-linux-bc6717d55d07110d8f3c6d31ec2af50c11b07091.zip | |
clocksource/drivers/timer-gx6605s: Fixup counter reload
When the timer counts to the upper limit, an overflow interrupt is
generated, and the count is reset with the value in the TIME_INI
register. But the software expects to start counting from 0 when
the count overflows, so it forces TIME_INI to 0 to solve the
potential interrupt storm problem.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Tested-by: Xu Kai <xukai@nationalchip.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/1597735877-71115-1-git-send-email-guoren@kernel.org
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions