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| author |   Lucas Stach <l.stach@pengutronix.de> | 2017-11-30 18:34:28 +0100 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-12-04 17:30:19 +0100 |
| commit | ca0e68e21aae10220eff71a297e7d794425add77 (patch) | |
| tree | d2bc5239f3e104575f6fde63d62fd0382f6a346f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | drm/tinydrm: add driver for ILI9225 panels (diff) | |
| download | wireguard-linux-ca0e68e21aae10220eff71a297e7d794425add77.tar.xz wireguard-linux-ca0e68e21aae10220eff71a297e7d794425add77.zip | |
drm/prime: skip CPU sync in map/unmap dma_buf
Dma-bufs should already be device coherent, as they are only pulled in the
CPU domain via the begin/end cpu_access calls. As we cache the mapping set
up by dma_map_sg a CPU sync at this point will not actually guarantee proper
coherency on non-coherent architectures, so we can as well stop pretending.
This is an important performance fix for architectures which need explicit
cache synchronization and userspace doing lots of dma-buf imports.
Improves Weston on Etnaviv performance 5x, where before this patch > 90%
of Weston CPU time was spent synchronizing caches for buffers which are
already device coherent.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20171130173428.8666-1-l.stach@pengutronix.de
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
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