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| author |   Val Packett <val@packett.cool> | 2024-12-05 15:29:36 -0300 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2025-02-26 17:52:48 +0100 |
| commit | d7169b8bcd855828cc691baee5e778af96855573 (patch) | |
| tree | 388d150956d49d68d2793b1ae90a4a2eabe49800 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 (diff) | |
| download | wireguard-linux-d7169b8bcd855828cc691baee5e778af96855573.tar.xz wireguard-linux-d7169b8bcd855828cc691baee5e778af96855573.zip | |
clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
RK3066 has two "CIF" video capture interface blocks, reference the
newly added IDs for their PCLK clocks.
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20241205182954.5346-2-val@packett.cool
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions