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| author |   Anson Huang <Anson.Huang@nxp.com> | 2018-06-03 09:44:04 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2018-06-29 11:41:19 -0700 |
| commit | debef195bd5c79210d60f1d6dec38bde3dae2b88 (patch) | |
| tree | 1f7c7e76d6a9f4f56bd635bfa349cca0397ab6de /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dt-bindings: clock: imx6ul: Do not change the clock definition order (diff) | |
| download | wireguard-linux-debef195bd5c79210d60f1d6dec38bde3dae2b88.tar.xz wireguard-linux-debef195bd5c79210d60f1d6dec38bde3dae2b88.zip | |
clk: imx6ul: add GPIO clock gates
i.MX6UL has GPIO clock gates in CCM CCGR,
add them into clock tree for clock management.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions