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author | 2019-04-14 22:23:21 +0300 | |
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committer | 2019-04-25 13:54:23 -0700 | |
commit | e71f4d385878671991e200083c7d30eb4ca8e99a (patch) | |
tree | ce71492050855769e843255e002e2360efcd16e7 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | clk: tegra: emc: Replace BUG() with WARN_ONCE() (diff) | |
download | wireguard-linux-e71f4d385878671991e200083c7d30eb4ca8e99a.tar.xz wireguard-linux-e71f4d385878671991e200083c7d30eb4ca8e99a.zip |
clk: tegra: divider: Mark Memory Controller clock as read-only
The Memory Controller (MC) clock rate can't be simply changed and nothing
in kernel need to change the rate, hence let's make the clock read-only.
This id also needed for the EMC driver because timing configuration may
require the MC clock diver to be disabled, that is handled by the EMC
clock / EMC driver integration and CLK framework shall not touch the
MC divider configuration on the EMC clock rate change.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions