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| author |   Matthias Schiffer <matthias.schiffer@ew.tq-group.com> | 2023-07-27 15:21:18 +0200 |
|---|---|---|
| committer |   Nishanth Menon <nm@ti.com> | 2023-08-05 12:03:49 -0500 |
| commit | ee1ada53846b6ff4154ac7a78b74a12cfd6a8639 (patch) | |
| tree | ab1bfcf7bd17303131bd12637bfe7f768e1ab69c /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI (diff) | |
| download | wireguard-linux-ee1ada53846b6ff4154ac7a78b74a12cfd6a8639.tar.xz wireguard-linux-ee1ada53846b6ff4154ac7a78b74a12cfd6a8639.zip | |
dt-bindings: arm: ti: Add compatible for AM642-based TQMaX4XxL SOM family and carrier board
For now only the MBaX4Xx carrier board is defined.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/e4283d6af59c77d2f690e070eb948dd9142a2276.1690463382.git.matthias.schiffer@ew.tq-group.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions