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| author |   Nicholas Piggin <npiggin@gmail.com> | 2019-06-28 15:33:32 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2019-07-02 21:39:49 +1000 |
| commit | f30a5e68f026f3214a9392391537adaa79996b24 (patch) | |
| tree | aae2e59629903f03e463e905cf59b3c2eb510288 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | powerpc/64s/exception: move SET_SCRATCH0 into EXCEPTION_PROLOG_0 (diff) | |
| download | wireguard-linux-f30a5e68f026f3214a9392391537adaa79996b24.tar.xz wireguard-linux-f30a5e68f026f3214a9392391537adaa79996b24.zip | |
powerpc/tm: update comment about interrupt re-entrancy
Since the system reset interrupt began to use its own stack, and
machine check interrupts have done so for some time, r1 can be
changed without clearing MSR[RI], provided no other interrupts
(including SLB misses) are taken.
MSR[RI] does have to be cleared when using SCRATCH0, however.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions