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author | 2021-03-10 14:04:31 +0200 | |
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committer | 2021-03-10 14:04:31 +0200 | |
commit | fbe8285d65a9e7c69fdbe6cc069d33581302c72d (patch) | |
tree | b3a65be80002486cdb257d6fd1669765a8e4cb1b /tools/perf/scripts/python/export-to-sqlite.py | |
parent | ARM: dts: Configure interconnect target module for omap4 mpu (diff) | |
download | wireguard-linux-fbe8285d65a9e7c69fdbe6cc069d33581302c72d.tar.xz wireguard-linux-fbe8285d65a9e7c69fdbe6cc069d33581302c72d.zip |
ARM: dts: Move omap4 mmio-sram out of l3 interconnect
We need mmio-sram early for omap4_sram_init() for IO barrier init, and
will be moving l3 interconnect to probe with simple-pm-bus that probes
at module_init() time. So let's move mmio-sram out of l3 to prepare for
that.
Otherwise we will get the following after probing the interconnects with
simple-pm-bus:
omap4_sram_init:Unable to get sram pool needed to handle errata I688
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions