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| author |   Shenming Lu <lushenming@huawei.com> | 2020-11-28 22:18:56 +0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2020-12-11 14:47:10 +0000 |
| commit | 0b39498230ae53e6af981141be99f4c7d5144de6 (patch) | |
| tree | 3f0629ad35d303ffedf4b195ececfac9b230cff6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | irqchip/alpine-msi: Fix freeing of interrupts on allocation error path (diff) | |
| download | wireguard-linux-0b39498230ae53e6af981141be99f4c7d5144de6.tar.xz wireguard-linux-0b39498230ae53e6af981141be99f4c7d5144de6.zip | |
irqchip/gic-v4.1: Reduce the delay when polling GICR_VPENDBASER.Dirty
The 10us delay of the poll on the GICR_VPENDBASER.Dirty bit is too
high, which might greatly affect the total scheduling latency of a
vCPU in our measurement. So we reduce it to 1 to lessen the impact.
Signed-off-by: Shenming Lu <lushenming@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20201128141857.983-2-lushenming@huawei.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions