diff options
| author |   Hanjun Guo <hanjun.guo@linaro.org> | 2019-03-05 21:40:58 +0800 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2019-03-19 14:55:10 +0000 |
| commit | 0ecc471a2cb7d4d386089445a727f47b59dc9b6e (patch) | |
| tree | edda8a42707c96a82cc21b4d2ff06b7e622abae9 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: Add MIDR encoding for HiSilicon Taishan CPUs (diff) | |
| download | wireguard-linux-0ecc471a2cb7d4d386089445a727f47b59dc9b6e.tar.xz wireguard-linux-0ecc471a2cb7d4d386089445a727f47b59dc9b6e.zip | |
arm64: kpti: Whitelist HiSilicon Taishan v110 CPUs
HiSilicon Taishan v110 CPUs didn't implement CSV3 field of the
ID_AA64PFR0_EL1 and are not susceptible to Meltdown, so whitelist
the MIDR in kpti_safe_list[] table.
Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
Reviewed-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangshaokun <zhangshaokun@hisilicon.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions