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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2022-11-03 21:55:42 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-11-08 14:23:59 +0100 |
| commit | 106f51e975608b4d55364b57071fbf60176c0d60 (patch) | |
| tree | a682856a62114ee501d742a63e9a9cd949c01650 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r8a779f0: Fix SCIF parent clocks (diff) | |
| download | wireguard-linux-106f51e975608b4d55364b57071fbf60176c0d60.tar.xz wireguard-linux-106f51e975608b4d55364b57071fbf60176c0d60.zip | |
clk: renesas: r8a779g0: Add TMU and SASYNCRT clocks
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103205546.24836-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions