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author | 2017-12-07 10:51:04 +0530 | |
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committer | 2017-12-18 10:44:09 +0530 | |
commit | 23059408b6a3c0960f4c7e46736228e5cbbe7d52 (patch) | |
tree | 981e1a72913448e24faaa23d59513d8d82f8656a /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma (diff) | |
download | wireguard-linux-23059408b6a3c0960f4c7e46736228e5cbbe7d52.tar.xz wireguard-linux-23059408b6a3c0960f4c7e46736228e5cbbe7d52.zip |
dmaengine: xilinx_dma: Fix race condition in the driver for multiple descriptor scenario
As per axi dmaengine spec the software must not move the tail pointer
to a location that has not been updated (next descriptor field of the
h/w descriptor should always point to a valid address).
When user submits multiple descriptors on the recv side, with the
current driver flow the last buffer descriptor next descriptor field
points to a invalid location, resulting the invalid data or errors from the
axidma dmaengine.
This patch fixes this issue by creating a buffer descritpor chain during
channel allocation itself and use those buffer descriptors for the
subsequent dma operations.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions