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| author |   Dinh Nguyen <dinguyen@kernel.org> | 2022-10-03 13:26:50 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-11-18 11:13:49 -0600 |
| commit | 3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1 (patch) | |
| tree | d71c942c03f064862d41b4867041a98d1e30a3cb /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm: dts: socfpga: remove "clk-phase" in sdmmc_clk (diff) | |
| download | wireguard-linux-3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1.tar.xz wireguard-linux-3b500ff37ce3ef5d7fbb731d082ef8f4cddce0f1.zip | |
arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node
The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
adjusted through the register in the system manager. Add the binding
"altr,sysmgr-syscon" to the SDMMC node for the driver to access the
system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
designate the smpsel and drvsel properties for the CIU clock.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions