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| author |   Aric Cyr <aric.cyr@amd.com> | 2021-03-17 13:57:49 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-04-20 21:40:55 -0400 |
| commit | 41ef8fbbef8e21e01c94105ed87b3a772b868439 (patch) | |
| tree | 58cb45b7d98a773f4982d1aaad0e84465ec2aad7 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | drm/amd/display: treat memory as a single-channel for asymmetric memory v2 (diff) | |
| download | wireguard-linux-41ef8fbbef8e21e01c94105ed87b3a772b868439.tar.xz wireguard-linux-41ef8fbbef8e21e01c94105ed87b3a772b868439.zip | |
drm/amd/display: Fix FreeSync when RGB MPO in use
[WHY]
We should skip programming manual trigger on non-primary planes when MPO is
enabled.
[HOW]
Implement an explicit mechanism for skipping manual trigger programming
for planes that shouldn't cause the frame to end.
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions