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| author |   Nicholas Piggin <npiggin@gmail.com> | 2021-04-02 12:41:24 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2021-04-18 23:19:29 +1000 |
| commit | 49c1d07fd04f54eb588c4a1dfcedc8d22c5ffd50 (patch) | |
| tree | 848a0382141cafb06180982674d8365f79b9cc5a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | powerpc/smp: Set numa node before updating mask (diff) | |
| download | wireguard-linux-49c1d07fd04f54eb588c4a1dfcedc8d22c5ffd50.tar.xz wireguard-linux-49c1d07fd04f54eb588c4a1dfcedc8d22c5ffd50.zip | |
powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors
Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt
mode for HV=1 interrupts. Instead, a new LPCR[HAIL] bit is defined
which behaves like AIL=3 for HV interrupts when set.
Set HAIL on bare metal to give us mmu-on interrupts and improve
performance.
This also fixes an scv bug: we don't implement scv real mode (AIL=0)
vectors because they are at an inconvenient location, so we just
disable scv support when AIL can not be set. However powernv assumes
that LPCR[AIL] will enable AIL mode so it enables scv support despite
HV interrupts being AIL=0, which causes scv interrupts to go off into
the weeds.
Fixes: 7fa95f9adaee ("powerpc/64s: system call support for scv/rfscv instructions")
Cc: stable@vger.kernel.org # v5.9+
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210402024124.545826-1-npiggin@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions