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| author |   Conor Dooley <conor.dooley@microchip.com> | 2022-11-09 21:22:18 +0000 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2022-11-15 16:48:02 +0100 |
| commit | 5836bf833a763e1573ce6fe5d0c310af23ebd49d (patch) | |
| tree | 2a56c0c58dcf04428bdc99cfefdab262859b2e66 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | MAINTAINERS: add entries for misc. RISC-V SoC drivers and devicetrees (diff) | |
| download | wireguard-linux-5836bf833a763e1573ce6fe5d0c310af23ebd49d.tar.xz wireguard-linux-5836bf833a763e1573ce6fe5d0c310af23ebd49d.zip | |
MAINTAINERS: generify the Microchip RISC-V entry name
These drivers work on our other FPGAs, for example the non-SoC PolarFire
connected to an FU-540 via chiplink. Make the entry a wee bit more
generic to match. While at it, remove the / from the heading so that it
matches other, neighbouring RISC-V entries.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221109212219.1598355-3-conor@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions