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| author |   Mark Tseng <chun-jen.tseng@mediatek.com> | 2023-11-16 19:04:46 +0800 |
|---|---|---|
| committer |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-12-11 11:36:11 +0100 |
| commit | 58dbf59308c903567c536f974c4dbc09fec90874 (patch) | |
| tree | a56e042cdbcb884294e4ac89628ec908c6f4e7ff /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | soc: mediatek: svs: Add support for MT8195 SoC (diff) | |
| download | wireguard-linux-58dbf59308c903567c536f974c4dbc09fec90874.tar.xz wireguard-linux-58dbf59308c903567c536f974c4dbc09fec90874.zip | |
soc: mediatek: svs: Add support for MT8186 SoC
MT8186 svs has a number of banks which used as optimization of opp
voltage table for corresponding dvfs drivers.
MT8186 svs big core uses 2-line high bank and low bank to optimize the
voltage of opp table for higher and lower frequency respectively.
Signed-off-by: Mark Tseng <chun-jen.tseng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions