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| author |   Tinghan Shen <tinghan.shen@mediatek.com> | 2023-09-01 16:09:32 +0800 |
|---|---|---|
| committer |   Mathieu Poirier <mathieu.poirier@linaro.org> | 2023-09-13 11:46:16 -0600 |
| commit | 5d5cfce48069df97ae83d001187f69d63b87242f (patch) | |
| tree | 3bd3f96a7a871ff2ec0ef11b3eb4de2aa505499b /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset (diff) | |
| download | wireguard-linux-5d5cfce48069df97ae83d001187f69d63b87242f.tar.xz wireguard-linux-5d5cfce48069df97ae83d001187f69d63b87242f.zip | |
remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout
The MT8195 SCP core 1 watchdog timeout needs to be handled in the
SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout
IRQ is wired on the same IRQ entry for core 0 watchdog timeout.
MT8195 SCP has a watchdog status register to identify the watchdog
timeout source when IRQ triggered.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230901080935.14571-12-tinghan.shen@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions