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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-06-09 16:32:30 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2021-06-10 15:35:57 +0200 |
| commit | 690ea5d394eb370973ffcb9ecda6a1855fe87d01 (patch) | |
| tree | 5a60b8116a3899c8bf2a9f5cc9b72b4b7f6bd591 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's (diff) | |
| download | wireguard-linux-690ea5d394eb370973ffcb9ecda6a1855fe87d01.tar.xz wireguard-linux-690ea5d394eb370973ffcb9ecda6a1855fe87d01.zip | |
arm64: dts: renesas: Add initial device tree for RZ/G2L SMARC EVK
Add basic support for RZ/G2L SMARC EVK (based on R9A07G044L2):
- memory
- External input clock
- SCIF
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210609153230.6967-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions