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author | 2025-03-24 14:33:23 +0100 | |
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committer | 2025-03-25 10:23:30 +0100 | |
commit | 6c963c42fc19d7c9ae9582ab75c3476d1752d979 (patch) | |
tree | dc028c1fc8163b24c3a06f162dcd58c4634c113b /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | x86/cacheinfo: Relocate CPUID leaf 0x4 cache_type mapping (diff) | |
download | wireguard-linux-6c963c42fc19d7c9ae9582ab75c3476d1752d979.tar.xz wireguard-linux-6c963c42fc19d7c9ae9582ab75c3476d1752d979.zip |
x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache()
Multiple code paths at cacheinfo.c and amd_nb.c check for AMD/Hygon CPUs
L3 cache presensce by directly checking leaf 0x80000006 EDX output.
Extract that logic into its own function. While at it, rework the
AMD/Hygon LLC topology ID caclculation comments for clarity.
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250324133324.23458-29-darwi@linutronix.de
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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