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author | 2020-05-30 09:40:12 +0200 | |
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committer | 2020-05-30 09:40:12 +0200 | |
commit | 76fe06c1e68b8f8dfb63d5b268623830dcb16ed0 (patch) | |
tree | 89b6e3df7c2ebdc996800429b3d30b7497f7ab7a /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | genirq: Check irq_data_get_irq_chip() return value before use (diff) | |
parent | dt-bindings: interrupt-controller: Add Loongson PCH MSI (diff) | |
download | wireguard-linux-76fe06c1e68b8f8dfb63d5b268623830dcb16ed0.tar.xz wireguard-linux-76fe06c1e68b8f8dfb63d5b268623830dcb16ed0.zip |
Merge tag 'irqchip-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates from Marc Zyngier:
- A few new drivers for the Loongson MIPS platform (HTVEC, PIC, MSI)
- A cleanup of the __irq_domain_add() API
- A cleanup of the IRQ simulator to actually use some of
the irq infrastructure
- Some fixes for the Sifive PLIC when used in a multi-controller
context
- Fixes for the GICv3 ITS to spread interrupts according to the
load of each CPU, and to honor managed interrupts
- Numerous cleanups and documentation fixes
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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