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| author |   Jiaxun Yang <jiaxun.yang@flygoat.com> | 2020-05-28 23:27:49 +0800 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2020-05-29 09:42:18 +0100 |
| commit | 818e915fbac518e8c78e1877a0048d92d4965e5a (patch) | |
| tree | f968276a5bf2203bffb46a5d351307aee5a3f630 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | irqchip/sifive-plic: Improve boot prints for multiple PLIC instances (diff) | |
| download | wireguard-linux-818e915fbac518e8c78e1877a0048d92d4965e5a.tar.xz wireguard-linux-818e915fbac518e8c78e1877a0048d92d4965e5a.zip | |
irqchip: Add Loongson HyperTransport Vector support
This controller appears on Loongson-3 chips for receiving interrupt
vectors from PCH's PIC and PCH's PCIe MSI interrupts.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200528152757.1028711-2-jiaxun.yang@flygoat.com
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions