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author | 2020-08-19 19:02:19 -0300 | |
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committer | 2020-08-30 19:58:50 +0800 | |
commit | 843b993c2d0b5e9aa22965234b914625ed3d3713 (patch) | |
tree | d5e089ef4500caf6f00b5dcee440555b36ad06fe /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | arm64: dts: imx8mp: Update pinfunc header file (diff) | |
download | wireguard-linux-843b993c2d0b5e9aa22965234b914625ed3d3713.tar.xz wireguard-linux-843b993c2d0b5e9aa22965234b914625ed3d3713.zip |
arm64: dts: imx8m: Fix the SPI chipselect polarity
The conversion of the spi-imx driver to use GPIO descriptors
in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors")
helped to detect the following SPI chipselect polarity mismatch on an
imx6q-sabresd for example:
[ 4.854337] m25p80@0 enforce active low on chipselect handle
Prior to the above commit, the chipselect polarity passed via cs-gpios
property was ignored and considered active-low.
The reason for such mismatch is clearly explained in the comments inside
drivers/gpio/gpiolib-of.c:
* SPI children have active low chip selects
* by default. This can be specified negatively
* by just omitting "spi-cs-high" in the
* device node, or actively by tagging on
* GPIO_ACTIVE_LOW as flag in the device
* tree. If the line is simultaneously
* tagged as active low in the device tree
* and has the "spi-cs-high" set, we get a
* conflict and the "spi-cs-high" flag will
* take precedence.
To properly represent the SPI chipselect polarity, change it to active-low
when the "spi-cs-high" property is absent.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions