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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-01-20 16:54:02 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-01-23 16:38:47 +0100 |
| commit | 88e7764497d48836f0f6684bda379c1c469b163b (patch) | |
| tree | bd4ffc834a3505d4dd226d2997b562670ad55f8c /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | ARM: dts: exynos: align HSOTG/USB node names (diff) | |
| download | wireguard-linux-88e7764497d48836f0f6684bda379c1c469b163b.tar.xz wireguard-linux-88e7764497d48836f0f6684bda379c1c469b163b.zip | |
ARM: dts: exynos: correct SATA clocks in Exynos5250
The DT schema expects clock name matching certain patterns:
exynos5250-smdk5250.dtb: sata@122f0000: clock-names:1: 'oneOf' conditional failed, one must be fixed:
'sclk_sata' is not one of ['pclk', 'aclk', 'hclk', 'sata']
'pmalive' was expected
'rxoob' was expected
'ref' was expected
Link: https://lore.kernel.org/r/20230120155404.323386-10-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions