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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-12 09:02:33 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-10-26 12:38:01 +0200 |
| commit | 99c05a2b710f16ea592ccb63ef5fe5f1f6b15db9 (patch) | |
| tree | 469de9ed36f08dd4f87442a36cf304633204a7a6 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | clk: renesas: r9a07g043: Drop WDT2 clock and reset entry (diff) | |
| download | wireguard-linux-99c05a2b710f16ea592ccb63ef5fe5f1f6b15db9.tar.xz wireguard-linux-99c05a2b710f16ea592ccb63ef5fe5f1f6b15db9.zip | |
clk: renesas: r8a779f0: Fix SD0H clock name
Correct the misspelled textual name of the SD0H clock.
Fixes: 9b5dd1ff705c6854 ("clk: renesas: r8a779f0: Add SDH0 clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/1f682d338f133608f138ae87323707436ad8c748.1665558014.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions