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author | 2023-01-25 10:45:09 +0100 | |
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committer | 2023-01-29 11:32:33 +0100 | |
commit | adf8238ef403190ffc1e60c0cfe3ea284b401314 (patch) | |
tree | e1ef5db8488263e76cf265fc6fca7f4cc38d0dc1 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | ARM: dts: exynos: move exynos-bus nodes out of soc in Exynos4210 (diff) | |
download | wireguard-linux-adf8238ef403190ffc1e60c0cfe3ea284b401314.tar.xz wireguard-linux-adf8238ef403190ffc1e60c0cfe3ea284b401314.zip |
ARM: dts: exynos: move exynos-bus nodes out of soc in Exynos4412
The soc node is supposed to have only device nodes with MMIO addresses,
as reported by dtc W=1:
exynos4412.dtsi:407.20-413.5:
Warning (simple_bus_reg): /soc/bus-acp: missing or empty reg/ranges property
and dtbs_check:
exynos4412-i9300.dtb: soc: bus-acp:
{'compatible': ['samsung,exynos-bus'], 'clocks': [[7, 456]], 'clock-names': ['bus'], 'operating-points-v2': [[132]], 'status': ['okay'], 'devfreq': [[117]]} should not be valid under {'type': 'object'}
Move the bus nodes and their OPP tables out of SoC to fix this.
Re-order them alphabetically while moving and put some of the OPP tables
in device nodes (if they are not shared).
Link: https://lore.kernel.org/r/20230125094513.155063-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
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